Generally, most failure analyzers for a semiconductor tester have only one control part for failure analysis. For this reason, in a plural-device test, it was hard to detect the failure position of all devices at once.
FIG. 4 shows an example of the conventional failure analyzer, generally used in the semiconductor test. This is a block diagram of four-device simultaneous measurement. Referring to FIG. 4, each of the devices under test (DUT), DUT#1.11 to DUT#4.14 outputs three signals: A, B and C. These output signals are provided to the comparator group 20 which compares these output signals with expected data, and, if a match does not occur, outputs a FAIL signal, that is, a failure signal.
An OR-gate 31 ORs the FAIL signals of DUT#1.11, and gives the OR data, a FOR1 signal to an AND gate 41 of a failure-masking section 40. In the same way, failure signals of DUT#2, #3 and #4 are ORed at OR-gates 32, 33 and 34, and then their ORed data are given to AND-gate 42, 43 and respectively. The outputs of AND-gates (41, 42 and 43) are applied to an OR-gate 45 to make a total failure signal STOR for all devices. Next, a data fail memory (DFM) control section 50 controls the total failure signal STOR and gives a store control (STC) signal to a failure memory 60.
By the way, the number of test patterns to compare with a device under test (hereinafter referred to as DUT) is 64 kH to 16 MW or more. Of the other hand, the capacity of failure memory is 1 kW at the most.
Regarding a difference between their capacity, in fact, there is possibility that all test patterns are used for a single-device failure analysis. However, such a small capacity has been suppose to be enough for the failure memory.
Here, the DFM control section 50 shown in FIG. 4 accepts the total failure signal; that is, OR-data of all devices failure signals, from the failure-masking section 40 and controls when to start or stop the failure memory, based on the number of patterns, pattern addresses and total failures. Because of the OR-data, however, the DFM control section 50 cannot identify which device the failure signal comes from.
The conventional failure analyzer can easily get information which only indicates that all the devices have passed or failed. However, to analyze the failure for each device, it had to measure plural times which is equivalent to the number of devices, invalidating unnecessary failure signals by using failure-masking function, which applies a mask signal to AND-gates (41, 42, 43 and 44) of failure-masking section 40. This process can identify a specific failure signal FORn to the DFM control section 50 which controls failure analysis.
Even if masking an arbitrary number of devices, however, the following problem occurs. FIG. 5 shows failure signals for each drive store signals produced by the failure signals. As shown in FIG. 5, since a device, DUT#2 is masked, a store signal STOR will not be generated for DUT#2. A store signal STOR of DUT#1A occurs first and enters to the DFM control section. Then other store signals occur in the order of DUT#4B, DUT#1B . . . . Here, if the failure memory is assumed to store eight data at a maximum, DUT#3's failure result which occurred at the ninth time cannot be stored into the failure memory.
Accordingly the conventional failure analyzer is suitable only for single-device failure analysis. If analyzing the failure of plural devices, it is necessary to apply the same test pattern for one of the plural devices while masking the other devices.